The trend toward smaller sizes, lighter weights and increased capabilities in electrical equipment has led to a shift in the dominant semiconductor mounting process from pin insertion to surface mounting. Progress of semiconductor devices toward a higher degree of integration entails the enlargement of dies having a size as large as 10 mm or more per side. For semiconductor devices using such large size dies, greater stresses are applied to the die and the sealant during solder reflow. Such stresses are problematic because separation occurs at the interface between the sealant and the die or substrate, the package cracks upon substrate mounting, and delamination and cracking occur after a thermal cycling test, leading to electrical failure.